This invention relates generally to semiconductor components, and relates more particularly to field effect transistors and methods of operation.
Power devices are electronic components designed to be tolerant of high current and voltage. Two parameters that affect the operating range of power devices are specific on-resistance (Rds (on)) and energy capability. Reductions in Rds (on) have led to significant advances in the technology of power devices, making possible the introduction of, for example, power lateral double-diffused metal-oxide-semiconductor (LDMOS) field-effect-transistor (FET) devices, referred to herein as power LDMOS devices and power FETs. As an example, power LDMOS devices can have drain-to-source breakdown voltages in the range of approximately 20-70 volts (V).
As the sizes of power LDMOS devices are reduced, however, the power densities of the power LDMOS devices increase, which introduces new challenges relative to energy capability optimization for the power LDMOS devices. More specifically, given two power LDMOS devices of differing sizes and exposing such devices to the same amount of power, the smaller power LDMOS device will less readily dissipate that power because it possesses less area in which to do so. The energy capability of power LDMOS devices in the 40-60 V range and in the presence of harsh operating environments is a key technological requirement. In fact many applications, among them automotive fuel injector drivers, airbag deployment equipment, and anti-lock braking systems, require that the size of power LDMOS devices be determined based on energy capability rather than Rds (on).
The energy capability of a power LDMOS device is the amount of power the device is able to absorb during a given length of time without being destroyed. This concept may be represented by the formula E=(P)(t), where xe2x80x9cExe2x80x9d represents energy, xe2x80x9cPxe2x80x9d represents power, and xe2x80x9ctxe2x80x9d represents time. Because power is equal to current (I) times voltage (V), the energy formula may be rewritten as E=(I)(V)(t), meaning that the energy capability of a power LDMOS device is related to the product of current, voltage, and time. Power LDMOS devices are constrained by natural material limitations of silicon and other semiconductor substances as to the amount of power or voltage such devices can absorb. This means that in order to maximize E, designers look for, among other things, ways to maximize the amount of voltage a power LDMOS device can safely withstand during a given length of time.
The energy capability of power LDMOS devices is limited by both thermal and electrical effects. The large amounts of energy involved in many power applications can cause the temperature of the power LDMOS device to increase dramatically, ultimately causing the failure of the device via thermal runaway. Device failure can also be induced electrically by snapback phenomena associated with the turn-on of a parasitic bipolar transistor within the power LDMOS device.
The destruction mechanism of a power LDMOS device, including both thermal and electrical effects as outlined in the preceding paragraph, is more fully discussed in xe2x80x9cExperimental and Theoretical Analysis of Energy Capability of RESURF LDMOSFETs and Its Correlation With Static Electrical Safe Operating Area (SOA),xe2x80x9d Khemka et al., IEEE Transactions on Electron Devices, Vol. 49, No. 6, June 2002, (the xe2x80x9cIEEE Publicationxe2x80x9d). The reader""s attention is particularly directed to Section IV of the IEEE Publication. The more power, or voltage and current, that is applied to a device, the higher its internal temperature will be. For a uniform power distribution across a power LDMOS device, the temperature profile peaks at a center of the device and falls off towards a periphery of the device. The center of a power LDMOS device, therefore, is typically the most problematic in terms of heat removal, and is where thermal breakdown is most likely to occur.
Various solutions to the thermal breakdown problem have been proposed. One such proposal is to place a thick metallization, possibly made of copper, on top of the integrated circuit (IC) that contains the power LDMOS device. The metallization is included for heat extraction purposes, but comes at the cost of including extra metal deposition, photolithographic masking, and etching steps, thus adding process complexity. Another proposal involves placing a bonding pad over the active area of the power LDMOS device to act as a heat sink. This solution is flawed because of the potential for damaging the active area of the power LDMOS device during a subsequent wire bonding process. All the existing solutions, including those outlined above, focus exclusively on alleviating the symptoms of the problem, and as such are limited in their effectiveness because such solutions do not address the cause of the problem. Therefore, a need exists for a method of operating a power LDMOS device that improves energy capability without increasing device cost, complexity, or size.